1. Field of the Invention
The present invention is related to analog to digital converter devices. More particularly, the present invention pertains to comparator devices used for digital signal generation.
2. Discussion of Related Art
The increasing importance of high-capacity wireless data communications has generated a demand for accurate, fast, and low-power-dissipation analog-to-digital converters to change high frequency analog inputs to digital signal formats. Delta-sigma modulators (DSMs) are often used to digitize signals having large dynamic range requirements, and have a wide variety of wireless applications, ranging from radar devices to low-power mobile communications. However, even though recent advances in very-large-scale circuit integration (VLSI) have provided low-cost, low-power implementations of the digital signal postprocessing associated with these DSMs, the comparator delay times and power parameters required for providing an adequate signal-to-noise ratio (SNR) for the DSMs has limited their usefulness.
A conventional delta-sigma modulator, shown in FIG. 1, uses one or more parallel comparator circuits 10 connecting a noise-shaping filter circuit 12, which provides the analog sum of an input signal stream Sin and respective analog feedback signals Fa, to the interface circuits 14 that produce one or more one-bit, two-level digital feedback signals Fb. The feedback signals F1, . . . Fn, provided as digital signals Fb by the interface circuits 14 in response to respective bit stream voltage signals Vb1, . . . Vbn output by the respective comparators 10, are converted to analog feedback signals Fn by respective digital to analog converters (DACs) 16 and fed back on respective paths to respective input points in the filter circuit 12, as is well-known in the art. The output of the DSM provides multiple digital output signal streams S1, . . . Sn in response to a sample clock signal having a given period Tc, and respective bit stream voltage signals Vb1, . . . Vbn. Each DSM comparator 10 shown in FIG. 1 has a respective distinctive trip-point threshold Th1, . . . Thn set by a respective input resistance value R1 . . . Rn.
Conventional comparator circuits 10 used in DSMs consist of a sequence of two or three transparent latch stages enabled by alternate phases of the sample clock signal Tc, as shown in FIGS. 1a and 1b. In FIG. 1, each comparator produces an output voltage Vb in each of the sampling intervals ti determined by the sample clock signal Tc, in response to the analog signal V(t) input by the filter circuit 12 to the comparator and the threshold Th of the individual comparator 10 determined by the respective resistance value R1, . . . Rn, so that each sample is quantized as one bit Vb(ti) in a digital bit stream bk for each of the intervals kti, as shown in FIG. 1c. Each bit Vb(ti) in the bit stream bk output by an ideal comparator is defined as:
                              b          k                =                  {                                                                                                                +                      1                                        ⁢                                                                                  ⁢                    if                    ⁢                                                                                  ⁢                                          V                      ⁡                                              (                        t                        )                                                                              ≤                  0                                                                                                                                                -                      1                                        ⁢                                                                                  ⁢                    if                    ⁢                                                                                  ⁢                                          V                      ⁡                                              (                        t                        )                                                                              >                  0                                                                                        (        1        )            However the performance limitations of conventional comparator circuits result in deviations from this ideal behavior. In particular, quantization latency Tq and the probability of a metastable state causing a comparator error Pmeta interact to limit the signal-to-noise SNR performance that can be achieved in DSM circuit designs having given frequency response and power efficiency parameters. The quantization latency Tq is the time that elapses between the occurrence of a sampled value at a time ti, and the occurrence of the smallest unambiguous comparator output voltage VL at the comparator output, which is shown schematically in FIG. 1c. 
It can be considered a given that output error probability is P=2VL/AQ, as explained by C. E. Woodward, et al. in IEEE Journal of Solid State Circuits, vol. SC-10 (December 1975) at p. 392. There, VL is the smallest unambiguous level for the comparator outputs Vb1 thru Vbn, Q is the least significant bit (LSB) voltage, e.g., the minimum value of the difference between the thresholds (Thi+1−Thi) corresponding to the resistances Ri, . . . Rn shown in FIG. 1, and A is the gain of a comparator 10. Then, where t is the time after a latch command provided by the clock signal Tc input to that comparator and τ is the regeneration time constant of the first latch stage 20 in that comparator:
  A  =      {                                                      A              o                        ,                          t              <              0                                                                                                      A                o                            ⁢                              ⅇ                                  t                  /                  τ                                                      ,                          t              ≥              0                                          Thus it can be demonstrated that, for input signal values V(t) that are uniformly distributed, the probability Pmeta is exponentially related to latency Tq:Pmeta=Po exp(−Tq/τ)  (2)
It is important to note that the value of the regeneration time constant τ in equation #2 is independent of Pmeta and Tq, and varies with the parasitic capacitances associated with the transistors in the first stage in a manner well-known in the art. Therefore Pmeta is an inverse function of Tq, when both are expressed as a multiples of τ, as is discussed in greater detail with reference to FIG. 5 below. Thus, in general, Pmeta increases as Tq decreases, and decreases as Tq increases, as shown in FIG. 3a, thereby providing a trade-off that sacrifices either frequency response or SNR, as indicated by FIG. 3b. 
This quantization latency Tq in a comparator's bit stream (bk) can be reduced, for low-frequency signals, without increasing Pmeta by adjusting the coupling of the respective feedback signal Fa into the filter circuit 12 from the interface circuits 14 in a manner well-known in the art. However, given that fc=1/Tc, at higher signal frequencies where Tq>Tc/2 that conventional compensation method is ineffective. The maximum usable signal frequency fmax provided by the conventional method is approximately:
                              f          max                ≈                  1                      4            ⁢                          T              q                                                          (        3        )            
Metastability errors are produced by the comparator's inability to promptly make a conclusive bit decision when the comparator's input sample V(t) is in a gray area Vg defined as Vg=2VL/Ao, where VL is the smallest unambiguous comparator output and Ao is the DC gain of the comparator. In this gray area Vg there is some small but significant probability that the output of the comparator will remain at an indeterminate level between the 0 and 1 digital states after the expected transition time Tr, as shown in FIG. 2b. Thus the metastability Pmeta of each comparator's digital output Vb is a function of what voltage V(t) is provided by the filtered analog signal input to that comparator input in each sampling interval ti.
Metastability is a critically important factor in the design of synchronizer circuits, where it compromises the reliability of the output signals' synchronization. In synchronizer circuit design, metastability has been measured as the number of indeterminate states occurring when a predetermined lag time is provided between the nominal clock pulse of the output of a synchronizer flipflop connected to the input of a second flipflop driven by a sample clock signal Tc. See J. U. Horstmann, et al., “Metastability Behavior of CMOS ASIC Flip-Flops in Theory and Test”, IEEE Journal of Solid State Circuits, vol. 24, no. 1 (February 1989), pp. 146–157. Ideally, of course, no errors would occur in the output that these synchronizers produce after the expected transition time Tr. Thus, in practice, metastability errors in these synchronizers can be reduced at the expense of an increase in quantization latency Tq from a point between ti and Tr to a later point, even beyond Tr in FIG. 2b. However, this reduces the suitability of these synchronizers for use in high-frequency applications, applications that implementing frequencies above the conventional fmax values provided by these circuits. This theoretical trade-off between latency and metastability is illustrated graphically in FIG. 3a. 
After all possible error corrections have been made, the SNR achievable by a DSM is a function of the probability of metastability error events Pmeta, as shown in FIG. 3b. Because all metastability errors are probabilistic rather than deterministic events, these errors cannot be effectively corrected or compensated, they must be prevented. See, J. A. Cherry et al., “Clock Jitter and Quantizer Metastability in Continuous-Time Delta-Sigma Modulators,” IEEE Transactions on Circuits and Systems, vol. 46 no. 6 (June 1999), pp. 661–676. However, to use DSMs in many popular applications, the DSMs' conventional Tq values must be reduced, not increased, so that fmax can be increased.
In FIG. 3b, the position of this SNR/Pmeta trade-off curve is independent of the interval Tc provided by the comparators' sample clock frequency fc. Instead, it is a function of the design parameters of the DSM circuit, particularly the permissible rate of power consumption, and the integrated circuit technology used to implement the modulator. Specifically, Tq and Pmeta in conventional comparator circuit designs are both a function of the number of latch stages (n) used in the comparator circuit, and can be expressed as:Tq=a+Tc(n−2)/2  (4)andPmeta=b exp(−c[a+Tc(n−2)/2])  (5)where the coefficients “a, b, c” are design-specific constants such that, where n is the number of latches and n≧2 they are: a=Tq for n=2, b=Po, c=1/τ. These constants are independent of the parameters affected by the present invention, and “exp” indicates that the subsequent parenthetical expression is an exponential function.
However, only a small subset of the points along the tradeoff curve shown in FIG. 3a are implemented by practice of adding latch stages to conventional comparator circuits, points that correspond to the cumulative delays produced by half-integer multiples of Tc, as shown in FIG. 4. The first two points correspond to the performance provided by two and three-stage implementations found in the prior art. The subsequent points in FIG. 4 correspond to additional latch stages proposed by J. A. Cherry, et al., (supra).
Continuous-time delta-sigma modulators (CT-DSMs), in particular, are advantageous for radar and popular low-power, high frequency digital mobile telecommunications applications because they can potentially provide higher resolution at a lower power consumption rate than discrete-time modulators. Unfortunately, the continuous-time DACs used in CT-DSMs increase the CT-DSMs' sensitivity to the metastability errors occurring during quantization. However, the additional stages proposed by J. A. Cherry, et al. to reduce metastability in continuous-time modulators significantly increase the modulators' power consumption. Thus, at least in theory, both the operating frequency and the power efficiency advantages of CT-DSMs are limited by the need to reduce the occurrence of metastability errors in CT-DSMs.
In low-pass DSM devices where fmin=0, the comparator latency Tq required to achieve an acceptable metastability error rate is a small fraction of the period of the highest signal frequency input to the modulator, reducing the probability Pmeta of sample values in grey area Vg. However, in band-pass modulators, where fmax≈fmin, the latency Tq may occupy a large portion of the period Tc available at center frequency (fctr) of the bandpass signal. As the latency approaches one-half of the period of output signal's frequency Tc/2, it becomes difficult to achieve stability in the feedback loop in these DSM devices.
The conventional trade-offs that increase quantization latency and the number of latch stages to reduce the incidence of these non-correctable probabilistic metastability errors in CT-DSMs reduce their operating frequency, and elevate the power consumption rate, respectively. Since many popular CT-DSM applications, such as the low-power, high-frequency GSM and PCS digital mobile telecommunications devices, require both increased high frequency capability and minimal power consumption, some other means of reducing metastability errors is needed.